Generally, lateral field effect transistors use an interdigitated layout with source, gate, and drain fingers side-by-side on a wafer front side. The interdigitated finger layout may be repeated for multiples of the source, gate and drain fingers. The fingers may be electrically connected to bond pads or to vertical vias that contact other metal layers or the backside of the wafer. Multiple fingers of a like designation (i.e., source, gate, and drain) may be electrically connected in parallel. Examples of lateral field effect transistors (FETs) include Silicon laterally diffused metal oxide semiconductor (LDMOS), gallium arsenide (GaAs) pseudomorphic high electron mobility transistors (pHEMT), and gallium nitride (GaN) HEMTs. FIG. 1 is a cross-sectional view depicting an active area of a GaN HEMT 10 that is typical of the prior art. GaN HEMT 10 includes a substrate 12, a buffer layer 14 disposed on top of the substrate 12, a GaN layer 16, and a device layer 18 made of aluminum gallium nitride (AlGaN). In this particular example, an outer surface of the AlGaN layer is a wafer front side 20. A source finger 22, a gate finger 24, and a drain finger 26 are disposed on the wafer front side 20 spaced from and parallel to each other. A width W is a greatest dimension of a transistor finger such as shown for the drain finger 26. In contrast, a length L is the minimum distance between the edges of a finger such as shown for the gate finger 24. Typically, the source finger 22, the gate finger 24, and the drain finger 26 have connections to bond pads or vias that are not shown in FIG. 1. The spacing between the source finger 22, the gate finger 24, and the drain finger 26 is determined by a required breakdown voltage limit, electrical field intensity limit, or photolithographic limit. A current flow and an on-resistance of a channel between the source finger 22 and the drain finger 26 are determined by properties of a semiconductor material making up the channel, the physical dimensions of the channel, an electrical contact resistance between the source finger 22 or the drain finger 26, and a semiconductor layer such as device layer 18. Moreover, other factors that affect the on-resistance of a channel include the ability of the gate finger 24, with proper bias, to control the depletion layer of the channel within the device layer 18.
In general, a larger active area created with wider fingers or greater numbers of narrow fingers will facilitate lower on-resistance and an ability to handle more current. A larger active area unfortunately means greater parasitic capacitance and inductance along with a larger and more expensive wafer die. Improved finger structures are needed to allow wider source, gate, and drain fingers without increasing an active area over the active area of a traditional FET.